1. Field of the Invention
The invention relates generally to a method of forming a multi-layer conductive line in a semiconductor device, and more particularly to, a method of forming a multi-layer conductive line capable of improving the reliability of the semiconductor device by preventing contamination problem due to Cu impurities and conductive line to conductive line leakage due to Cu re-deposition within a dual damascene pattern.
2. Description of the Prior Art
Generally, in semiconductor devices, electron devices, or the like, the technology in which a conductive film such as aluminum (A1), tungsten (W), or the like is deposited on an insulating film and the conductive film is then patterned by common photolithography process and dry etching process to form a conductive line, has been widely used as the technology for forming the conductive line. In particular, as an effort to reduce a RC delay time in logic devices of the semiconductor device that requires a high speed, a research on the use of a metal such as copper (Cu) having a low resistivity as the conductive line instead of aluminum (A1) or tungsten (W) has recently been made.
In the process of forming the conductive line using copper (Cu), however, as the patterning process of Cu: is difficult compared to those of A1 or W, a process by which a trench is formed and the trench is then buried to form the conductive line, so called xe2x80x98a damascene processxe2x80x99 has been used. The damascene process can be classified into a single damascene process by which a via hole is formed, the via hole is filled with a conductive material for a via and the trench for the conductive line is then formed to bury the conductive line, and a dual damascene process by which the via hole and the trench are formed and the via hole and the trench for the conductive line are then simultaneously filled with a material for the conductive line.
If the multi-layer conductive line is formed using the dual damascene process, in an unit process constituting the dual damascene process, when a chemical mechanical polishing (CMP) process for forming a lower conductive line and a dual frequency etch process for pre-cleaning a contact portion between the lower conductive line and an upper conductive line are performed, contaminant of the lower conductive line, for example, copper (Cu) contaminant when the lower conductive line is formed using Cu, remains on the surface of the interlayer insulating film and on the side wall within the dual damascene pattern (i.e., including a via hole and a trench). These Cu impurities may degrade the leakage characteristic of the semiconductor device. Thus, in order to manufacture a reliable semiconductor device, an effective process control is necessarily required. Further, as the interlayer insulating films of the semiconductor device are replaced by thin films of a low dielectric constant having a porous property in a dense SiO2 series, a problem such as decrease in the reliability of the semiconductor device due to the Cu impurities becomes further important. Accordingly, in order to solve the above problems, a cleaning process and a process of forming an anti-diffuse film have been brought out as an important issue in the process of manufacturing the multi-layer conductive line.
The present invention is contrived to solve the above problems and an object of the present invention is to improve the reliability of a semiconductor device by preventing contamination problem due to Cu impurities and the conductive line to conductive line leakage due to re-deposition of Cu within the dual damascene pattern.
Another object of the present invention is to prevent increase in a RC delay due to an increased dielectric constant when a multi-layer conductive line is formed.
Still another object of the present invention is to inhibit decrease in the yield of a via hole, by preventing void generating within the via hole when the multi-layer conductive line is formed.
Further another object of the present invention is to improve the yield of the Cu conductive line, by inhibiting decrease in the yield of the via hole and also preventing diffusion of Cu atoms.
Another object of the present invention is to prevent penetration of Cu atoms due to a subsequent annealing process, by preventing re-deposition of the Cu atoms on the inner side wall of the via hole during the conventional argon (Ar) sputtering process.
In order to accomplish the above object, the method of forming the multi-layer conductive line according to the present invention, is characterized in that it comprises the steps of forming a lower conductive line on a semiconductor substrate in which a lower layer is formed, performing a wet cleaning process to remove impurities remaining on the entire structure and etch an exposed portion of the lower conductive line, performing a selective growth process to form a sacrificial barrier layer at the etched portion of the lower conductive line that was etched in the step of performing the wet cleaning process, forming an interlayer insulating film on the entire structure, etching the interlayer insulating film by means of a dual damascene process so that the sacrificial barrier layer is exposed, to form a dual damascene pattern, and depositing an electroplating film to bury the dual damascene pattern and then performing a chemical mechanical polishing process to form an upper conductive line.